//------------------------------------------------------------
//  Filename: s_reset.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2019-04-26 23:16
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module S_RESET ( 
    input wire clk,      // 59Mhz
    input wire sclk,
    input wire reset_i,  // 0 - active
      
    output reg reset_n
);      

//--------------------------------------------------------
localparam RESET_TIME = 500000; //5s
localparam ONE_SECOND = 250000;//1s
//--------------------------------------------------------
reg [7:0] raw_value0;
reg [7:0] raw_value1;
reg [31:0]reset_cycle;
wire      raw_value0_set = (raw_value0 !== 8'h5A)?1'b1:1'b0;
wire      raw_value1_set = (raw_value1 !== 8'hF0)?1'b1:1'b0;
//--------------------------------------------------------
always @(posedge sclk) begin
    if(raw_value0 !== 8'h5A) begin 
        raw_value0 <= 8'h5A;    
    end 
end 
//--------------------------------------------------------
always @(posedge clk) begin
    if(raw_value1 !== 8'hF0) begin 
        raw_value1 <= 8'hF0;    
    end 
end 
//--------------------------------------------------------
always @(posedge clk) begin
    if(raw_value0_set||raw_value1_set||(reset_i == 0))begin 
        reset_cycle <= 0;    
    end 
    else if(reset_cycle < RESET_TIME ) begin 
        reset_cycle <= reset_cycle + 1;     
    end 
end 
//--------------------------------------------------------
always @(posedge clk) begin
    if(raw_value0_set||raw_value1_set||(reset_cycle < RESET_TIME))begin 
        reset_n <= 0;    
    end 
    else begin 
        reset_n <= 1;  
    end 
end 
      
endmodule
